1. Field of the Invention
The present invention relates to a technique for forming a capacitor and, more particularly, to a technique for forming a capacitor having a pair of electrodes each made of a polycrystalline semiconductor.
2. Description of the Background Art
FIGS. 28 through 38 are schematic sectional views showing a background art method of manufacturing a capacitor in a step-by-step manner. A structure in which a base layer 1, a semiconductor oxide film 3, a semiconductor film 4 and a semiconductor nitride film 5 are stacked in the order named is prepared, as shown in FIG. 28. The base layer 1 is made of, e.g., silicon, and the semiconductor oxide film 3 is made of, e.g., silicon oxide. The semiconductor film 4 is made of, e.g., polycrystalline silicon (polysilicon), and the semiconductor nitride film 5 is made of, e.g., silicon nitride.
Next, using a photolithographic technique, etching is performed upon the structure shown in FIG. 28 to selectively remove the semiconductor oxide film 3, the semiconductor film 4, the semiconductor nitride film 5 and the base layer 1, thereby forming trenches 6, as shown in FIG. 29.
Then, a semiconductor oxide film 14 made of, e.g., silicon oxide is deposited on the structure shown in FIG. 29. The trenches 6 are filled with the semiconductor oxide film 14. A photolithographic technique is used to selectively remove the semiconductor oxide film 14. Specifically, a portion of a surface of the semiconductor nitride film 5 which is spaced not less than a predetermined distance x apart from the trenches 6 is selectively exposed. This provides a structure shown in FIG. 30.
Next, chemical-mechanical polishing (CMP) is performed to remove other semiconductor oxide film 14 than fills the trenches 6. The semiconductor nitride film 5 and the semiconductor film 4 are removed by using wet etching. The remaining portions of the semiconductor oxide film 14 subjected to these processes become isolation oxide films 2 shown in FIG. 31.
A photolithographic technique and an impurity implantation process are used to form a P well 21 and an N well 22 shown in FIG. 32 in an upper surface of the base layer 1 under the isolation oxide films 2 and the semiconductor oxide film 3.
A polycrystalline semiconductor film having a thickness of about 1000 angstroms is deposited on the structure shown in FIG. 32. The polycrystalline semiconductor film is made of, e.g., doped polysilicon. A removal process using a photolithographic process is performed so that the polycrystalline semiconductor film remains selectively over the P well 21 (on the opposite side of the P well 21 from the base layer 1). This provides a structure shown in FIG. 33. The remaining portion of the polycrystalline semiconductor film serves as a lower electrode 23 of a capacitor to be described later.
Next, a semiconductor oxide film 8, a semiconductor nitride film 9 and a semiconductor oxide film 10 are deposited in the order named on the structure shown in FIG. 33. The semiconductor oxide film 8, the semiconductor nitride film 9 and the semiconductor oxide film 10 are, e.g., 200, 300 and 500 angstroms, respectively, in thickness. A photolithographic technique is used to selectively remove the semiconductor oxide film 10 so that the semiconductor oxide film 10 remains only over the lower electrode 23. The dimension of the remaining portion of the semiconductor oxide film 10 is smaller than that of the lower electrode 23. Thereafter, using the remaining portion of the semiconductor oxide film 10 as a mask, wet etching is performed to selectively remove the semiconductor oxide film 8 and the semiconductor nitride film 9. This provides a structure shown in FIG. 34. The remaining portions of the semiconductor oxide film 8 and semiconductor nitride film 9 function as a dielectric layer 24 of the capacitor to be described later.
The semiconductor oxide film 3, which has been damaged by the processes performed thus far, is removed by wet etching. In this process, the remaining portion of the semiconductor oxide film 10 is also removed. An oxidation process is performed anew to form an oxide film 11 on the upper surfaces of the P well 21 and the N well 22. This provides a structure shown in FIG. 35. The oxide film 11 functions also as a gate oxide film of a MOS transistor to be described later.
Next, a polycrystalline semiconductor film 13 is deposited on the structure shown in FIG. 35. The polycrystalline semiconductor film 13 is made of, e.g., polysilicon. A photolithographic technique is used to selectively remove the polycrystalline semiconductor film 13 so that portions of the polycrystalline semiconductor film 13 remain on the oxide film 11 and the isolation oxide film 2 over the P and N wells 21 and 22 in spaced apart relation to the lower electrode 23, and on the semiconductor nitride film 9. The dimension of the portion of the polycrystalline semiconductor film 13 remaining on the semiconductor nitride film 9 is smaller than that of the semiconductor nitride film 9. This provides a structure shown in FIG. 36. The portion of the polycrystalline semiconductor film 13 remaining on the semiconductor nitride film 9 is subjected to ion implantation to be described below to thereby function as an upper electrode which, in conjunction with the lower electrode 23, constitutes the capacitor with the dielectric layer 24 therebetween. The portion of the polycrystalline semiconductor film 13 remaining on the oxide film 11 and the isolation oxide film 2 is subjected to ion implantation to be described below to thereby function as a gate electrode of a MOS transistor which forms a channel in the upper surface of each of the P well 21 and the N well 22 thereunder. The portion of the polycrystalline semiconductor film 13 functioning as the gate electrode of an NMOS transistor to be formed in the P well 21 is not shown in FIG. 36.
Thereafter, ions are implanted into the remaining portions of the polycrystalline semiconductor film 13 and the oxide film 11 over the P well 21 and the N well 22 to form a source/drain region 26, a gate electrode 29, and an upper electrode 25 of the capacitor shown in FIG. 37. The gate electrode of the MOS transistor to be formed in the P well 21 and the source/drain region of the MOS transistor to be formed in the N well 22 are not shown in the sectional view of FIG. 37.
The source/drain regions of the MOS transistors are exposed by the selective removal of the semiconductor oxide film 11 thereover. Silicide films 28 are formed on the exposed surfaces of the source/drain regions and the gate electrodes. In the ion implantation process, sidewalls 27 made of, e.g., TEOS may be used as a mask in addition to a mask using a resist to be described later. The removal of the resist provides a structure shown in FIG. 37.
Next, an interlayer insulation film 30 made of, e.g., silicon oxide is deposited on the entire top surface, and chemical-mechanical polishing is performed to planarize the surface of the interlayer insulation film 30. A photolithographic technique is used to form contact holes for electrical connections to the source/drain region 26, the gate electrode 29, and the upper and lower electrodes 25 and 23 of the capacitor. Barrier metals 35 are formed in the respective contact holes. Electrodes 36 are formed which fill the respective contact holes with the barrier metals 35 therebetween and protrude from the surface of the interlayer insulation film 30.
In general, the base layer 1 in the step shown in FIG. 28 has a flat surface, and the upper electrode 25 and the gate electrode 29 are formed from the polycrystalline semiconductor film 13. Thus, a distance D0 (see FIG. 36) between the upper electrode 25 and the gate electrode 29 at their farthest locations from the base layer 1 as measured in the thickness direction of the base layer 1 is approximately equal to the sum of the thickness of the lower electrode 23 and the thickness of the dielectric layer 24. In the above example, the topmost portion of the gate electrode 29 is about 1500 angstroms below the topmost portion of the upper electrode 25 because the lower electrode 23, the semiconductor oxide film 8 and the semiconductor nitride film 9 are about 1000, 200 and 300 angstroms, respectively, in thickness.
A resist 50 serving as a mask is used in the ion implantation for the formation of the upper electrode 25, the source/drain region 26 and the gate electrode 29. FIG. 39 is a sectional view schematically showing the resist 50. The resist 50 has a substantially flat surface independently of the surface asperities of an object to be covered by the resist 50. The patterning to be actually used is not shown in FIG. 39, and hence the resist 50 is shown as formed entirely without any specified position to be opened therein.
In view of the foregoing, a thickness D1 (see FIG. 39) of the resist 50 on the topmost portion of the polycrystalline semiconductor film 13 remaining over the lower electrode 23 is about 1500 angstroms less than a thickness D2 of the resist 50 on the topmost portion of the polycrystalline semiconductor film 13 remaining over the N well 22. Thus, the resist 50 tends to have an increased thickness in order to cover the capacitor.
However, since the resist 50 functions as a mask during the ion implantation as mentioned above, the increased thickness of the resist 50 gives rise to the shadowing effect and the degradation of patterning accuracy.
The polishing for planarization of the interlayer insulation film 30 must be controlled so as not to expose the upper electrode 25, rather than the gate electrode 29. Further, since the upper electrode 25 of the capacitor is formed at a position high above the base layer 1, the interlayer insulation film 30 need to be formed thick. This requires prolonged etching for the formation of a contact hole 33 for electrical connection to the source/drain region 26. On the other hand, a contact hole 32 for electrical connection to the upper electrode 25 is shallower than the contact hole 33, as shown in FIG. 38, and the depth difference between the contact holes 32 and 33 is as large as 2000 angstroms. For this reason, the prolonged etching for reliable formation of the contact hole 33 is liable to cause overetching for the formation of the contact hole 32, resulting in the removal of the silicide film 28 on the upper electrode 25. The removal of the silicide film 28 on the upper electrode 25 presents the problem of the increase in electric resistance between the electrode filling the contact hole 32 and the upper electrode 25.
It is therefore an object of the present invention to provide a technique for reducing the height of a capacitor above a substrate.
The present invention is intended for a method of manufacturing a capacitor. According to the present invention, the method includes steps (a) through (d). In the step (a), a trench is formed in a surface of a substrate. In the step (b), an insulation film filling the trench is formed. In the step (c), the insulation film is selectively removed to form an isolating insulation film in the trench. The isolating insulation film has a recess on an opposite side from the substrate. The recess has a bottom deeper than the surface of the substrate. In the step (d), a lower electrode is formed on the bottom, a dielectric layer is formed on the lower electrode, and an upper electrode is formed on the dielectric layer.
The method can reduce a distance from the substrate to the upper electrode. The thickness of a resist for use in a subsequent photolithographic technique is accordingly reduced. This reduces the shadowing effect and the degradation of patterning accuracy when performing the photolithographic technique.
Additionally, in an interlayer insulation film to be formed subsequently, the depth of a contact hole for electrical connection to the upper electrode is made approximately equal to the depth of a contact hole for electrical connection to other portions. This solves a problem such that overetching of the contact hole for electrical connection to the upper electrode occurs to increase an electric resistance.
Moreover, since the recess is provided in the isolating insulation film selectively provided in the substrate, there is no need to polish the insulation film from which the isolating insulation film is formed, after the formation of the lower electrode. Therefore, the lower electrode is not polished.
Preferably, the step (b) includes steps (b-1) and (b-2). In the step (b-1), the insulation film is selectively etched to reduce the thickness of a portion of the insulation film spaced not less than a predetermined distance apart from the trench. In the step (b-2), the insulation film is polished to form the isolating insulation film having the recess in the trench. The step (b-2) is performed after the step (b-1).
The method can easily form the isolating insulation film having the recess by utilizing dishing caused by polishing of the insulation film.
Preferably, the substrate is devoid of any semiconductor device disposed near the trench.
The method does not provide a semiconductor device to be influenced by dishing.
Preferably, the insulation film is removed in the center of the trench to define the recess in the step (b-1).
The method can easily form the isolating insulation film having the recess because the insulation film is removed also in the center of the trench.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.